In the manufacture of semiconductor memories defects are frequently encountered that afflict a limited number of memory elements in a memory matrix. The reason for the high probability of defects of this type resides in that in a semiconductor memory device the greatest part of the chip area is occupied by the memory matrix; moreover, it is in the memory matrix, and not in the peripheral circuitry, that the manufacturing process characteristics are usually pushed to limits.
In order to avoid that the presence of a limited number of defective matrix memory elements on many millions forces the rejection of the entire chip, and therefore to increase the manufacturing process yield, the technique is known of providing for the manufacture of a certain number of additional memory elements, commonly called "redundancy memory elements," to be used as a replacement of those matrix memory elements that, during testing of the memory device, prove defective; the selection circuits, with which the integrated component must necessarily be provided, and which allow the above-mentioned functional replacement of a defective matrix memory element with a redundancy memory element are indicated as a whole with the name of "redundancy circuitry," while the set of redundancy memory elements and circuitry is defined for short as "redundancy."
The redundancy circuitry comprises programmable non-volatile memory registers suitable to store those address configurations corresponding to the defective matrix memory elements; such registers are programmed once and for all during the memory device testing, and must retain the information stored therein even in absence of the power supply.
Each non-volatile memory register must therefore be made up of a number of programmable memory cells at least equal to the number of address bits which allows the selection of the matrix memory elements. Each memory cell of a memory register is therefore dedicated to store the logical state of a particular address bit of the address configuration corresponding to a defective matrix memory element, and comprises at least one programmable non-volatile memory element, a circuit for programming the memory element, a circuit for reading the information stored in the memory element and a circuit for comparing said information with the current logical state of the address bit associated to the memory cell.
Since however even unprogrammed non-volatile memory registers, associated to unused redundancy memory elements, store a particular address configuration, i.e., they store that particular address configuration corresponding to the unprogrammed condition of the memory cells, when a non-defective matrix memory element is addressed whose address coincides with the logical configuration of the memory cells in an unprogrammed memory register, the redundancy memory element associated to said unprogrammed register will be selected instead of the non-defective matrix memory element. If in a memory device two or more redundancy memory elements are not used, since the unprogrammed condition is the same for all the memory cells of the non-volatile memory registers, addressing the non-defective matrix memory element whose address coincides with the configuration of the unprogrammed memory cells would cause said two or more redundancy memory elements to be selected simultaneously.
To prevent such unacceptable simultaneous selection, each non-volatile memory register is provided with an additional programmable memory cell (called "guard memory cell" or "control memory cell") which allows the selection of the associated redundancy memory element only in the case it is programmed. This however causes a significant increase in the overall chip area.
In order to evaluate the degree of defectiveness of the manufacturing process, or of a given fabrication lot of memory device chips, it is useful to know for each chip how many redundancy memory elements have been utilized to replace defective matrix memory elements, in other words to perform a "resources check."
According to a known technique, this can be done by putting the memory device in a particular test mode in which all the selection signals for the redundancy memory elements generated by the non-volatile memory registers are ORed together and the resulting signal is supplied to one output buffer driving an output pad of the memory device; the memory device is then sequentially supplied with all the possible address configurations; each time an address configuration corresponding to a defective matrix memory element which has been replaced by a redundancy memory element is supplied to the memory device, the corresponding non-volatile register will activate the selection signal for the redundancy memory element, and this occurrence will be detected by the testing machine by sensing the logical state of said output pad. A given non-volatile memory register will activate the corresponding selection signal only if the current address configuration supplied to the memory device coincides with that stored in it, and if the respective guard memory cell is programmed.
This is a lengthy procedure, especially for dense memory devices, wherein the possible address configurations can be several millions; furthermore, the testing machine must keep track of the number of times the output pad changes its logical state.
In the copending European Patent Application No. 93830491.2 in the name of the same Applicant, a redundancy circuitry is described wherein no guard memory cells are required in the non-volatile memory registers; this is achieved by means of the generation of an inhibition signal which inhibits the activation of the selection signals for the redundancy memory elements each time the memory device is supplied with an address configuration coincident with the logical state stored in a non-programmed non-volatile memory register.